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课计算机组成原理课件第3章MainContent•CharacteristicsofMemorySystem•TypesofMemory•TheMemoryHierarchy•CacheMemory•VirtualMemoryCharacteristicsofMemo

rySystemsLocationCPUInternalExternalCapacityWordByteInternalUsuallygovernedbydatabuswidthExternalUsuallyablockwhichismuchlargert

hanawordUnitofTransferAccessMethods(1)SequentialStartatthebeginningandreadthroughinorderAccesstim

edependsonlocationofdataandpreviouslocatione.g.tapeDirectIndividualblockshaveuniqueaddressAccessi

sbyjumpingtovicinityplussequentialsearchAccesstimedependsonlocationandpreviouslocatione.g.diskCharacteristicsofMemo

rySystemsRandomIndividualaddressesidentifylocationsexactlyAccesstimeisindependentoflocationorpreviou

saccesse.g.RAMAssociativeDataislocatedbyacomparisonwithcontentsofaportionofthestoreAccesstimeisindependentoflocationorpreviousaccesse.

g.cacheAccessMethods(2)CharacteristicsofMemorySystemsPerformanceAccesstimeTimebetweenpresentingtheaddressandgettingthevaliddata

MemoryCycletimeTimemayberequiredforthememoryto“recover”beforenextaccessCycletimeisaccess+recoveryTransferRateRa

teatwhichdatacanbemovedCharacteristicsofMemorySystemsPhysicalTypesSemiconductorRAMMagneticDisk&TapeOpticalCD&DVDOthers

HologramCharacteristicsofMemorySystemsTheBottomLineHowmuch?(Capacity)Greatercapacity,smallercostperbitGreat

ercapacity,sloweraccesstimeHowfast?(Accesstime)Fasteraccesstime,greatercostperbitHowexpensive?(Cost)M

emoryHierarchyRegistersInCPUInternalorMainmemoryMayincludeoneormorelevelsofcache“RAM”ExternalmemoryBackingstoreHierarchyListRegistersL1Cach

eL2CacheMainmemoryDiskOpticalTapeMemoryHierarchy-DiagramHierarchyListCacheSmallamountoffastmemorySitsbetweennormalmainmemoryand

CPUMaybelocatedonCPUchipormoduleContentaddressablememoryWhatmakescache“special”?Cacheisnotaccessedbyaddress;itisac

cessedbycontent.Forthisreason,cacheissometimescalledcontentaddressablememoryorCAM.TerminologyHit:Therequesteddatare

sidesinagivenlevelofmemory.Miss:Therequesteddataisnotfoundinthegivenlevelofmemory.HitRate:Thepercentageofmemor

yaccessesfoundinagivenlevelofmemory.MissRate:Thepercentageofmemoryaccessesnotfoundinagivenlevelofmemory.MissRate=1-HitR

ateHitTime:Thetimerequiredtoaccesstherequestedinformationinagivenlevelofmemory.MissPenalty:Thetimerequiredtop

rocessamiss,whichincludesreplacingablockinanupperlevelofmemory,plustheadditionaltimetodelivertherequest

eddatatotheprocessor.Cache/MainMemoryStructureCacheoperation–overviewCPUrequestscontentsofmemorylocationCheckcacheforthisdataIfpresent,ge

tfromcache(fast)Ifnotpresent,readrequiredblockfrommainmemorytocacheThendeliverfromcachetoCPUCacheincludestagstoidentifywhichblockofm

ainmemoryisineachcacheslotCacheReadOperation-FlowchartTypicalCacheOrganizationCacheDesignSizeMappingFunction

ReplacementAlgorithmWritePolicyBlockSizeNumberofCachesCacheSizeSmallenoughsooverallcost/bitisclosetotha

tofmainmemoryLargeenoughsooverallaverageaccesstimeisclosetothatofthecachealoneAccesstime=mainmemoryaccesstimepluscacheaccesstimeLar

gecachestendtobeslightlyslowerthansmallcachesItisimpossibletoarriveatasingle“optimum”cachesizeComparisonofCacheSi

zesProcessorTypeYearofIntroductionL1cacheaL2cacheL3cacheIBM360/85Mainframe196816to32KB——PDP-11/70Minicomputer19751KB——VAX11/780Minicomputer197

816KB——IBM3033Mainframe197864KB——IBM3090Mainframe1985128to256KB——Intel80486PC19898KB——PentiumPC19938KB/8KB256to512KB—PowerPC601PC

199332KB——PowerPC620PC199632KB/32KB——PowerPCG4PC/server199932KB/32KB256KBto1MB2MBIBMS/390G4Mainframe199732KB256KB2MBIBMS/390G6M

ainframe1999256KB8MB—Pentium4PC/server20008KB/8KB256KB—IBMSPHigh-endserver/supercomputer200064KB/32KB

8MB—CRAYMTAbSupercomputer20008KB2MB—ItaniumPC/server200116KB/16KB96KB4MBSGIOrigin2001High-endserver200132KB/32KB4MB—Itanium2PC/server200232KB256KB6M

BIBMPOWER5High-endserver200364KB1.9MB36MBCRAYXD-1Supercomputer200464KB/64KB1MB—MappingFunctionTheelementsincludedinth

efollowingexample:Cacheof64kByteCacheblockof4bytesi.e.cacheis16k(214)linesof4bytes16MBytesmainmemory24bitaddress(224=

16M)1.DirectMapping2.AssociativeMapping3.SetAssociativeMappingDirectMappingDirectMappingEachblockofmainmemorymapstoonlyonecac

helinei.e.ifablockisincache,itmustbeinonespecificplacei=jmodmWherei=cachelinenumberj=mainmemoryblocknumberm=numberof

linesinthecacheDirectMappingAddressisintwopartsLeastSignificantwbitsidentifyuniquewordMostSignifi

cantsbitsspecifyonememoryblockTheMSBsaresplitintoacachelinefieldrandatagofs-r(mostsignificant)Cachem=2rDirectMappingCacheLineTableCachelineM

ainMemoryblocksheld00,m,2m,3m…2s-m11,m+1,2m+1…2s-m+1m-1m-1,2m-1,3m-1…2s-1DirectMappingAddressStructureTags-rLineorSlotrWordw814224bitaddress

2bitwordidentifier(4byteblock)22bitblockidentifier8bittag(=22-14)14bitslotorlineNotwoblocksinthesameli

nehavethesameTagfieldCheckcontentsofcachebyfindinglineandcheckingTagDirectMappingCacheOrganizationD

irectMappingExampleDirectMappingSummaryAddresslength=(s+w)bitsNumberofaddressableunits=2s+wwordsorbytesBlocksize=linesize=2wwordsorbytesNumberofb

locksinmainmemory=2s+w/2w=2sNumberoflinesincache=m=2rSizeoftag=(s–r)bitsDirectMappingpros&consSimpleInexpensiv

eFixedlocationforgivenblockIfaprogramaccesses2blocksthatmaptothesamelinerepeatedly,cachemissesareveryhighAssociativ

eMappingAmainmemoryblockcanloadintoanylineofcacheMemoryaddressisinterpretedastagandwordTaguniquelyidentifiesblockof

memoryEveryline’stagisexaminedforamatchCachesearchinggetsexpensiveAssociativeMappingAssociativeMapping024631570246315781012141191315LineNumber

BlockTagCacheMemoryAssociativeCacheOrganizationAssociativeMappingExampleTag22bitWord2bitAssociativeMappingAd

dressStructure22bittagstoredwitheach32bitblockofdataComparetagfieldwithtagentryincachetocheckforhitLeastsignificant2bitsofaddressidentifywhi

ch16bitwordisrequiredfrom32bitdatablocke.g.AddressTagDataCachelineFFFFFCFFFFFC246824683FFFAssociativeMappingSummaryAddressleng

th=(s+w)bitsNumberofaddressableunits=2s+wwordsorbytesBlocksize=linesize=2wwordsorbytesNumberofblocksinm

ainmemory=2s+w/2w=2sNumberoflinesincache=undeterminedSizeoftag=sbitsSetAssociativeMappingCacheisdividedintoanumbe

rofsetsEachsetcontainsanumberoflinesAgivenblockmapstoanylineinagivensete.g.BlockBcanbeinanylineofsetie.g.2linesperset2way

associativemappingAgivenblockcanbeinoneof2linesinonlyonesetSetAssociativeMappingSetAssociativeMappingBlockLineNumberCacheMemory02463157Set0Se

t1Set2Set30246315781012141191315KWaySetAssociativeCacheOrganizationSetAssociativeMappingAddressStructureUsesetfieldtodeterminecaches

ettolookinComparetagfieldtoseeifwehaveahite.gAddressTagDataSetnumber1FF7FFC1FF123456781FFF0017FFC001112233441FFFTag9bitSet13bi

tWord2bitSetAssociativeMappingExample13bitsetnumber000000,008000,018000,FF8000…maptosamesetTwoWaySetAssociativeMappingExampleTw

oWaySetAssociativeMappingExampleSetAssociativeMappingSummaryAddresslength=(s+w)bitsNumberofaddressableunits=2s+wwor

dsorbytesBlocksize=linesize=2wwordsorbytesNumberofblocksinmainmemory=2s+w/2w=2sNumberoflinesinset=kNumberofsets=v=2dNumberoflinesincache=k×

v=k×2dSizeoftag=(s–d)bitsSetAssociativeMappingSummaryWhenv=m,k=1,thesetassociativemappingreducestodirectmapping.Whenv

=1,k=m,thesetassociativemappingreducestoassociativemapping.Theuseoftwolinesperset(v=m/2,k=2)isthecommonsetassociativemappingorganization.Replace

mentAlgorithms(1)DirectmappingNochoiceEachblockonlymapstoonelineReplacethatlineReplacementAlgorithms

(2)Associative&SetAssociativeHardwareimplementedalgorithm(speed)LeastRecentlyused(LRU)e.g.in2waysetassociativeWhicho

fthe2blockisLRU?Firstinfirstout(FIFO)replaceblockthathasbeenincachelongestLeastfrequentlyusedreplaceblockwh

ichhashadfewesthitsRandomWritePolicyMustnotoverwriteacacheblockunlessmainmemoryisuptodateMultipleCPUsmayhaveindividualcachesI/Omayaddressm

ainmemorydirectlyWritethroughAllwritesgotomainmemoryaswellascacheMultipleCPUscanmonitormainmemorytraffictokee

plocal(toCPU)cacheuptodateLotsoftrafficSlowsdownwritesWritebackUpdatesinitiallymadeincacheonlyUpdatebitforcacheslotissetwhenupdateocc

ursIfblockistobereplaced,writetomainmemoryonlyifupdatebitissetOthercachesgetoutofsyncI/OmustaccessmainmemorythroughcacheLineSize(块的大小)Astheblock

sizeincreasesfromverysmalltolargersizes,thehitratewillatfirstincreasebecausethedatainthevicinityofareferencedwordarelikelytoberef

erencedinthenearfuture.Thehitratewillbegintodecrease,astheblockbecomesevenbigger.64~128bytecachelinesizesaremostfrequentlyused.

NumberofCachesMultilevelCaches(L1/L2)On-chipCacheOff-chipCacheSplitCachesDataCacheInstructionCache

Pentium4Cache80386–noonchipcache80486–8kusing16bytelinesandfourwaysetassociativeorganizationPentium(allversions)–twoonchipL1caches

Data&instructionsPentiumIII–L3cacheaddedoffchipPentium4L1caches8kbytes64bytelinesfourwaysetassociativeL2cache256

k128bytelines8waysetassociativeL3cacheonchipIntelCacheEvolutionProblemSolutionProcessoronwhichfeaturefirstappears

Externalmemoryslowerthanthesystembus.Addexternalcacheusingfastermemorytechnology.386Increasedprocessorspeedresultsinexternalbusbecomingabottleneckfor

cacheaccess.Moveexternalcacheon-chip,operatingatthesamespeedastheprocessor.486Internalcacheisrathersmall,duetolimitedspaceonc

hipAddexternalL2cacheusingfastertechnologythanmainmemory486ContentionoccurswhenboththeInstructionPrefetcherandtheExecutionU

nitsimultaneouslyrequireaccesstothecache.Inthatcase,thePrefetcherisstalledwhiletheExecutionUnit’sdataaccesstakesplace.Createseparateda

taandinstructioncaches.PentiumIncreasedprocessorspeedresultsinexternalbusbecomingabottleneckforL2cacheaccess.Createseparateback-sidebusthatrunsathigh

erspeedthanthemain(front-side)externalbus.TheBSBisdedicatedtotheL2cache.PentiumProMoveL2cacheontotheprocessorchip

.PentiumIISomeapplicationsdealwithmassivedatabasesandmusthaverapidaccesstolargeamountsofdata.Theon-chipcachesaretoosmall.Add

externalL3cache.PentiumIIIMoveL3cacheon-chip.Pentium4PowerPCCacheOrganization601–single32kb8waysetassociat

ive603–16kb(2x8kb)twowaysetassociative604–32kb620–64kbG3&G464kbL1cache8waysetassociative256k,512kor1ML2cachetwowaysetassociativeG5

32kBinstructioncache64kBdatacacheVirtualMemoryThepurposeofvirtualmemoryistousetheharddiskasanextensio

nofRAM,thusincreasingtheavailableaddressspaceaprocesscanuse.Themostcommonwaytoimplementvirtualmemoryisusing

paging,amethodinwhichmainmemoryisdividedintofixed-sizeblocksandprogramsaredividedintothesamesizebloc

ks.VirtualMemoryEachprogramhasapagetableassociatedwithitthatmapseachprogrampagetoamemorypageframe.Thus,logical

addressesinaprogramareinterpretedasaphysicaladdress--pageframenumberandanoffsetwithinthepage.VirtualMemorySupposeaprogramis16byt

eslong,hasaccesstoan8-bytememorythatusesbytesaddressing,andapageis2bytesinlength.Astheprogramexecutes,itgeneratesthefollowingaddr

essesreferencestring:0,1,2,3,6,7,10,11.ReviewQuestions(思考题)CHAPTER01.Explainthepurposeofvirtualmemoryandcac

he.2.Explainhowassociativemappingcacheisdifferentfromdirectmappingcache.NextLessonCHAPTER0ControlUnit（控制单

元）ControlUnitOperationMicroprogrammedControl