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课计算机组成原理课件第3章MainContent•CharacteristicsofMemorySystem•TypesofMemory•TheMemoryHierarchy•CacheMemory•VirtualMemoryCharacteristicsofMemorySystemsL

ocationCPUInternalExternalCapacityWordByteInternalUsuallygovernedbydatabuswidthExternalUsuallyablockwhic

hismuchlargerthanawordUnitofTransferAccessMethods(1)SequentialStartatthebeginningandreadthroughinorderAccesstimedependsonlocationofdataa

ndpreviouslocatione.g.tapeDirectIndividualblockshaveuniqueaddressAccessisbyjumpingtovicinityplussequentialsearchAccesstimedependsonlocation

andpreviouslocatione.g.diskCharacteristicsofMemorySystemsRandomIndividualaddressesidentifylocationsexactlyAccesstimeisin

dependentoflocationorpreviousaccesse.g.RAMAssociativeDataislocatedbyacomparisonwithcontentsofaportion

ofthestoreAccesstimeisindependentoflocationorpreviousaccesse.g.cacheAccessMethods(2)CharacteristicsofMemorySystemsPerforman

ceAccesstimeTimebetweenpresentingtheaddressandgettingthevaliddataMemoryCycletimeTimemayberequiredfortheme

moryto“recover”beforenextaccessCycletimeisaccess+recoveryTransferRateRateatwhichdatacanbemovedCharacteristicso

fMemorySystemsPhysicalTypesSemiconductorRAMMagneticDisk&TapeOpticalCD&DVDOthersHologramCharacteristicsofMemorySyst

emsTheBottomLineHowmuch?(Capacity)Greatercapacity,smallercostperbitGreatercapacity,sloweraccesstimeHowfast?(Accesstime)Fasteraccesstime,greater

costperbitHowexpensive?(Cost)MemoryHierarchyRegistersInCPUInternalorMainmemoryMayincludeoneormorelevelsofcache“RA

M”ExternalmemoryBackingstoreHierarchyListRegistersL1CacheL2CacheMainmemoryDiskOpticalTapeMemoryHierarchy-DiagramHierarchyListCacheSmall

amountoffastmemorySitsbetweennormalmainmemoryandCPUMaybelocatedonCPUchipormoduleContentaddressablememor

yWhatmakescache“special”?Cacheisnotaccessedbyaddress;itisaccessedbycontent.Forthisreason,cacheissometimescalledcontentaddressab

lememoryorCAM.TerminologyHit:Therequesteddataresidesinagivenlevelofmemory.Miss:Therequesteddataisnotfoundinthegivenlevelofmemory.HitR

ate:Thepercentageofmemoryaccessesfoundinagivenlevelofmemory.MissRate:Thepercentageofmemoryaccessesnotfoundinagivenlevelofmemory.Mi

ssRate=1-HitRateHitTime:Thetimerequiredtoaccesstherequestedinformationinagivenlevelofmemory.MissPenalty:Thetimere

quiredtoprocessamiss,whichincludesreplacingablockinanupperlevelofmemory,plustheadditionaltimetodelivertherequesteddatatotheprocessor.Cach

e/MainMemoryStructureCacheoperation–overviewCPUrequestscontentsofmemorylocationCheckcacheforthisdataIfpresent,getf

romcache(fast)Ifnotpresent,readrequiredblockfrommainmemorytocacheThendeliverfromcachetoCPUCacheincludestagstoide

ntifywhichblockofmainmemoryisineachcacheslotCacheReadOperation-FlowchartTypicalCacheOrganizationCacheDesignSizeMappingFunctio

nReplacementAlgorithmWritePolicyBlockSizeNumberofCachesCacheSizeSmallenoughsooverallcost/bitisclosetothatofmainmemoryLargeenoughsoover

allaverageaccesstimeisclosetothatofthecachealoneAccesstime=mainmemoryaccesstimepluscacheaccesstimeLar

gecachestendtobeslightlyslowerthansmallcachesItisimpossibletoarriveatasingle“optimum”cachesizeComparisonofCac

heSizesProcessorTypeYearofIntroductionL1cacheaL2cacheL3cacheIBM360/85Mainframe196816to32KB——PDP-11/70Minicomputer19

751KB——VAX11/780Minicomputer197816KB——IBM3033Mainframe197864KB——IBM3090Mainframe1985128to256KB——Intel80486PC19898KB——Pentium

PC19938KB/8KB256to512KB—PowerPC601PC199332KB——PowerPC620PC199632KB/32KB——PowerPCG4PC/server199932KB/32KB256KBto1MB2MBIBMS/390G4Ma

inframe199732KB256KB2MBIBMS/390G6Mainframe1999256KB8MB—Pentium4PC/server20008KB/8KB256KB—IBMSPHigh-endserver/supercomputer200064KB/32KB8MB—CRAYM

TAbSupercomputer20008KB2MB—ItaniumPC/server200116KB/16KB96KB4MBSGIOrigin2001High-endserver200132KB/32KB4MB—Itanium2PC/server2

00232KB256KB6MBIBMPOWER5High-endserver200364KB1.9MB36MBCRAYXD-1Supercomputer200464KB/64KB1MB—MappingFunctionTheelementsincludedinthefoll

owingexample:Cacheof64kByteCacheblockof4bytesi.e.cacheis16k(214)linesof4bytes16MBytesmainmemory24bitaddress(224=1

6M)1.DirectMapping2.AssociativeMapping3.SetAssociativeMappingDirectMappingDirectMappingEachblockofmainmemorymapstoonlyonecachelinei.e.ifabl

ockisincache,itmustbeinonespecificplacei=jmodmWherei=cachelinenumberj=mainmemoryblocknumberm=numberofline

sinthecacheDirectMappingAddressisintwopartsLeastSignificantwbitsidentifyuniquewordMostSignificantsbitsspecifyonememoryblockTheMSBsarespli

tintoacachelinefieldrandatagofs-r(mostsignificant)Cachem=2rDirectMappingCacheLineTableCachelineMainMemoryblocksheld00,m,2m,3m…2s-m11,m+1

,2m+1…2s-m+1m-1m-1,2m-1,3m-1…2s-1DirectMappingAddressStructureTags-rLineorSlotrWordw814224bitaddress2bitwordident

ifier(4byteblock)22bitblockidentifier8bittag(=22-14)14bitslotorlineNotwoblocksinthesamelinehavethesameTagfieldCheckcontentsofcach

ebyfindinglineandcheckingTagDirectMappingCacheOrganizationDirectMappingExampleDirectMappingSummaryAddresslength=(s+w)bitsN

umberofaddressableunits=2s+wwordsorbytesBlocksize=linesize=2wwordsorbytesNumberofblocksinmainmemory=2s+w/2w=2sNumberoflinesincache=m=2rSizeoftag=

(s–r)bitsDirectMappingpros&consSimpleInexpensiveFixedlocationforgivenblockIfaprogramaccesses2blockst

hatmaptothesamelinerepeatedly,cachemissesareveryhighAssociativeMappingAmainmemoryblockcanloadintoanylineofcacheMemoryaddressisinterp

retedastagandwordTaguniquelyidentifiesblockofmemoryEveryline’stagisexaminedforamatchCachesearchinggetsexpensiveAssociativeMappingAssocia

tiveMapping024631570246315781012141191315LineNumberBlockTagCacheMemoryAssociativeCacheOrganizationAssociativeMappingExampleTag22bi

tWord2bitAssociativeMappingAddressStructure22bittagstoredwitheach32bitblockofdataComparetagfieldwithtagentryincach

etocheckforhitLeastsignificant2bitsofaddressidentifywhich16bitwordisrequiredfrom32bitdatablocke.g.AddressTagDataCachelineFFFFFCFFFFFC246824683

FFFAssociativeMappingSummaryAddresslength=(s+w)bitsNumberofaddressableunits=2s+wwordsorbytesBlocksize=line

size=2wwordsorbytesNumberofblocksinmainmemory=2s+w/2w=2sNumberoflinesincache=undeterminedSizeoftag=sbitsSetAssociativeMappingCacheisdivided

intoanumberofsetsEachsetcontainsanumberoflinesAgivenblockmapstoanylineinagivensete.g.BlockBcanbeinanylineofseti

e.g.2linesperset2wayassociativemappingAgivenblockcanbeinoneof2linesinonlyonesetSetAssociativeMappi

ngSetAssociativeMappingBlockLineNumberCacheMemory02463157Set0Set1Set2Set30246315781012141191315KWaySetAssociativeCacheOrganizationSetAs

sociativeMappingAddressStructureUsesetfieldtodeterminecachesettolookinComparetagfieldtoseeifwehaveahite.gAddressTagDataSetnumber1FF7FFC1FF12

3456781FFF0017FFC001112233441FFFTag9bitSet13bitWord2bitSetAssociativeMappingExample13bitsetnumber000000,008000,018000,FF8000…

maptosamesetTwoWaySetAssociativeMappingExampleTwoWaySetAssociativeMappingExampleSetAssociativeMappingSummaryAddresslength

=(s+w)bitsNumberofaddressableunits=2s+wwordsorbytesBlocksize=linesize=2wwordsorbytesNumberofblocksinmainmemory=2s

+w/2w=2sNumberoflinesinset=kNumberofsets=v=2dNumberoflinesincache=k×v=k×2dSizeoftag=(s–d)bitsSetAssociativeMappingSummaryWhen

v=m,k=1,thesetassociativemappingreducestodirectmapping.Whenv=1,k=m,thesetassociativemappingreducestoassociativemapping.

Theuseoftwolinesperset(v=m/2,k=2)isthecommonsetassociativemappingorganization.ReplacementAlgorithms(1)DirectmappingNochoiceEachbl

ockonlymapstoonelineReplacethatlineReplacementAlgorithms(2)Associative&SetAssociativeHardwareimplementedalgori

thm(speed)LeastRecentlyused(LRU)e.g.in2waysetassociativeWhichofthe2blockisLRU?Firstinfirstout(FIFO)replace

blockthathasbeenincachelongestLeastfrequentlyusedreplaceblockwhichhashadfewesthitsRandomWritePolicyMustnot

overwriteacacheblockunlessmainmemoryisuptodateMultipleCPUsmayhaveindividualcachesI/Omayaddressmainmemorydirectl

yWritethroughAllwritesgotomainmemoryaswellascacheMultipleCPUscanmonitormainmemorytraffictokeeplocal(toCP

U)cacheuptodateLotsoftrafficSlowsdownwritesWritebackUpdatesinitiallymadeincacheonlyUpdatebitforcacheslotissetwhenupdateoc

cursIfblockistobereplaced,writetomainmemoryonlyifupdatebitissetOthercachesgetoutofsyncI/OmustaccessmainmemorythroughcacheLineSi

ze(块的大小)Astheblocksizeincreasesfromverysmalltolargersizes,thehitratewillatfirstincreasebecausethedatainth

evicinityofareferencedwordarelikelytobereferencedinthenearfuture.Thehitratewillbegintodecrease,astheblockbecom

esevenbigger.64~128bytecachelinesizesaremostfrequentlyused.NumberofCachesMultilevelCaches(L1/L2)On-chipCache

Off-chipCacheSplitCachesDataCacheInstructionCachePentium4Cache80386–noonchipcache80486–8kusing16bytelines

andfourwaysetassociativeorganizationPentium(allversions)–twoonchipL1cachesData&instructionsPentiumIII–L3cachea

ddedoffchipPentium4L1caches8kbytes64bytelinesfourwaysetassociativeL2cache256k128bytelines8waysetassociativeL3cacheonchipIntelCacheEvol

utionProblemSolutionProcessoronwhichfeaturefirstappearsExternalmemoryslowerthanthesystembus.Addextern

alcacheusingfastermemorytechnology.386Increasedprocessorspeedresultsinexternalbusbecomingabottleneckforcacheaccess.M

oveexternalcacheon-chip,operatingatthesamespeedastheprocessor.486Internalcacheisrathersmall,duetolimitedspaceonchipAddexternalL2cach

eusingfastertechnologythanmainmemory486ContentionoccurswhenboththeInstructionPrefetcherandtheExecutionUnitsi

multaneouslyrequireaccesstothecache.Inthatcase,thePrefetcherisstalledwhiletheExecutionUnit’sdataaccesstakesplace.Createseparatedataandins

tructioncaches.PentiumIncreasedprocessorspeedresultsinexternalbusbecomingabottleneckforL2cacheaccess.Createseparateback-sidebust

hatrunsathigherspeedthanthemain(front-side)externalbus.TheBSBisdedicatedtotheL2cache.PentiumProMoveL2cacheonto

theprocessorchip.PentiumIISomeapplicationsdealwithmassivedatabasesandmusthaverapidaccesstolargeamountsofdata.Theon-chipcachesaretoosma

ll.AddexternalL3cache.PentiumIIIMoveL3cacheon-chip.Pentium4PowerPCCacheOrganization601–single32kb8waysetassociative603–16kb(2x8kb)twoway

setassociative604–32kb620–64kbG3&G464kbL1cache8waysetassociative256k,512kor1ML2cachetwowaysetassociativ

eG532kBinstructioncache64kBdatacacheVirtualMemoryThepurposeofvirtualmemoryistousetheharddiskasanextensionofRAM,thusincreasingthe

availableaddressspaceaprocesscanuse.Themostcommonwaytoimplementvirtualmemoryisusingpaging,amethodinwhichmainmemoryisdividedintof

ixed-sizeblocksandprogramsaredividedintothesamesizeblocks.VirtualMemoryEachprogramhasapagetableassociatedw

ithitthatmapseachprogrampagetoamemorypageframe.Thus,logicaladdressesinaprogramareinterpretedasaphysicaladdress--pageframenumbe

randanoffsetwithinthepage.VirtualMemorySupposeaprogramis16byteslong,hasaccesstoan8-bytememorythatusesbytesaddressing,andapageis2bytesinlength.A

stheprogramexecutes,itgeneratesthefollowingaddressesreferencestring:0,1,2,3,6,7,10,11.ReviewQuestions(思考题

)CHAPTER01.Explainthepurposeofvirtualmemoryandcache.2.Explainhowassociativemappingcacheisdifferentfromdirectmappingcache.NextLessonCHAPTE

R0ControlUnit（控制单元）ControlUnitOperationMicroprogrammedControl