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1第十四章：CMOS基本工艺流程现代CMOS工艺基本流程2SiliconSubstrateP+~2um~725umSiliconEpiLayerP−选择衬底•晶圆的选择–掺杂类型（N或P）–电阻率（掺杂浓度）–晶向•高掺杂(P+)的Si晶圆•低掺杂(P−)的Si外延层3SiliconSubs

trateP+SiliconEpiLayerP−PadOxide热氧化•热氧化–形成一个SiO2薄层，厚度约20nm–高温，H2O或O2气氛–缓解后续步骤形成的Si3N4对Si衬底造成的应力4SiliconSubs

trateP+SiliconEpiLayerP-SiliconNitrideSi3N4淀积•Si3N4淀积–厚度约250nm–化学气相淀积(CVD)–作为后续CMP的停止层5SiliconSubstrateP+

SiliconEpiLayerP-SiliconNitridePhotoresist光刻胶成形•光刻胶成形–厚度约0.5~1.0um–光刻胶涂敷、曝光和显影–用于隔离浅槽的定义6SiliconSubstrateP+SiliconEpiLayerP-Silicon

NitridePhotoresistSi3N4和SiO2刻蚀•Si3N4和SiO2刻蚀–基于氟的反应离子刻蚀(RIE)7SiliconSubstrateP+SiliconEpiLayerP-SiliconNitridePhotoresistTransi

storActiveAreasIsolationTrenches隔离浅槽刻蚀•隔离浅槽刻蚀–基于氟的反应离子刻蚀(RIE)–定义晶体管有源区8SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideTransistorActiveAreasIs

olationTrenches除去光刻胶•除去光刻胶–氧等离子体去胶，把光刻胶成分氧化为气体9SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideFuturePMOSTransisto

rSiliconDioxideFutureNMOSTransistorNocurrentcanflowthroughhere!SiO2淀积•SiO2淀积–用氧化物填充隔离浅槽–厚度约为0.5~1.0um，和浅槽深度和几何形状有关–化学气相淀积(CVD)10SiliconSubstrateP+

SiliconEpiLayerP-SiliconNitrideFuturePMOSTransistorFutureNMOSTransistorNocurrentcanflowthroughhere!化学机械抛光•化学机械抛光(CMP)–CMP除去表面的氧化层–到Si3N4层为

止11SiliconSubstrateP+SiliconEpiLayerP-FuturePMOSTransistorFutureNMOSTransistor除去Si3N4•除去Si3N4–热磷酸(H3PO4)湿法刻蚀，约180℃12TrenchOxideCrossS

ectionBareSilicon平面视图•完成浅槽隔离(STI)13SiliconSubstrateP+SiliconEpiLayerP-FuturePMOSTransistorFutureNMOSTransistorPhotoresist光刻胶

成形•光刻胶成形–厚度比较厚，用于阻挡离子注入–用于N-阱的定义14SiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorPhotoresistN-WellPhosphorous(-)Ions磷离子注入•磷离子注入–高能磷离子注入–形

成局部N型区域，用于制造PMOS管15SiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorN-Well除去光刻胶16PhotoresistSiliconSubstr

ateP+SiliconEpiLayerP-FutureNMOSTransistorN-Well光刻胶成形•光刻胶成形–厚度比较厚，用于阻挡离子注入–用于P-阱的定义17SiliconSubstrateP+SiliconEpi

LayerP-PhotoresistN-WellBoron(+)IonsP-Well•硼离子注入–高能硼离子注入–形成局部P型区域，用于制造NMOS管硼离子注入18SiliconSubstrateP+SiliconEpiLayerP-N-WellP-Well除去光

刻胶19SiliconSubstrateP+SiliconEpiLayerP-P-WellN-Well退火•退火–在600~1000℃的H2环境中加热–修复离子注入造成的Si表面晶体损伤–注入杂质的电激活–同时会造成杂质的进一步扩散–快速加热工艺(RTP)可以减少杂质的

扩散20TrenchOxideN-WellP-WellCrossSection•完成N-阱和P-阱平面视图21SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSacrificialOxide牺牲氧化层生长•牺牲氧化层生长–厚度约2

5nm–用来捕获Si表面的缺陷22SiliconSubstrateP+SiliconEpiLayerP-P-WellN-Well除去牺牲氧化层•除去牺牲氧化层–HF溶液湿法刻蚀–剩下洁净的Si表面23SiliconSubstrateP+SiliconEpiLayerP-P-WellN

-WellGateOxide栅氧化层生长•栅氧化层生长–工艺中最关键的一步–厚度2~10nm–要求非常洁净，厚度精确(±1Å)–用作晶体管的栅绝缘层24SiliconSubstrateP+SiliconEp

iLayerP-P-WellN-WellPolysilicon多晶硅淀积•多晶硅淀积–厚度150~300nm–化学气相淀积(CVD)25SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistChannel

LengthPolysilicon光刻胶成形•光刻胶成形–工艺中最关键的图形转移步骤–栅长的精确性是晶体管开关速度的首要决定因素–使用最先进的曝光技术——深紫外光(DUV)–光刻胶厚度比其他步骤薄26SiliconSubstrateP+SiliconEpiLayerP-P-Well

N-WellPhotoresistChannelLength多晶硅刻蚀•多晶硅刻蚀–基于氟的反应离子刻蚀(RIE)–必须精确的从光刻胶得到多晶硅的形状27SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellGateOxid

ePolyGateElectrode除去光刻胶28TrenchOxideN-WellP-WellCrossSectionPolysilicon平面视图•完成栅极29SiliconSubstrateP+Silico

nEpiLayerP-P-WellN-WellGateOxidePolyGateElectrodePolyRe-oxidation多晶硅氧化•多晶硅氧化–在多晶硅表面生长薄氧化层–用于缓冲隔离多晶硅和

后续步骤形成的Si3N430SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresist光刻胶成形•光刻胶成形–用于控制NMOS管的衔接注入31SiliconSubstrate

P+SiliconEpiLayerP-P-WellN-WellPhotoresistArsenic(-)IonsNTipNMOS管衔接注入•NMOS管衔接注入–低能量、浅深度、低掺杂的砷离子注入–衔接注入用于削弱栅区的热载流子效应32S

iliconSubstrateP+SiliconEpiLayerP-P-WellN-WellNTip除去光刻胶33SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotore

sistNTip光刻胶成形•光刻胶成形–用于控制PMOS管的衔接注入34SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistBF2(+)IonsNTipPTip•PMOS管衔接注入–低能量、浅

深度、低掺杂的BF2+离子注入–衔接注入用于削弱栅区的热载流子效应PMOS管衔接注入35SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellNTipPTip除去光

刻胶36SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSiliconNitrideThinnerHereThickerHereNTipPTipPTipSi3N4淀积•Si3N

4淀积–厚度120～180nm–CVD37SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSpacerSidewallNTipPTipPTipSi3N4刻蚀•Si3N4刻

蚀–水平表面的薄层Si3N4被刻蚀，留下隔离侧墙–侧墙精确定位晶体管源区和漏区的离子注入–RIE38SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistNTipPTip光刻胶成形•光刻胶成形–用于控制NMOS

管的源/漏区注入39SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistArsenic(-)IonsN+DrainN+SourcePTipNMOS管源/漏注入

•NMOS管源/漏注入–浅深度、重掺杂的砷离子注入，形成了重掺杂的源/漏区–隔离侧墙阻挡了栅区附近的注入40SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourcePTip除去光刻胶41SiliconS

ubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourcePhotoresistPTip光刻胶成形•光刻胶成形–用于控制PMOS管的源/漏区注入42SiliconSubstrateP+SiliconEpiLayerP-P-WellN-Wel

lBF2(+)IonsPhotoresistN+DrainN+SourceP+SourceP+DrainPMOS管源/漏注入•PMOS管源/漏注入–浅深度、重掺杂的BF2+离子注入，形成了重掺杂的源/漏

区–隔离侧墙阻挡了栅区附近的注入43SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+SourceP+DrainLightlyDoped“Tips”除去光刻胶和退火•除去光刻胶和退火–用RTP工艺，消除杂质在源/漏区

的迁移44TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacer平面视图•完成晶体管源/漏极，

电子器件形成45SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+Source除去表面氧化物•除去表面氧化物–在HF溶液中快速浸泡，使栅、源、漏区的Si暴露出来46Sil

iconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitaniumTi淀积•Ti淀积–厚度20~40nm–溅射工艺–Ti淀积在整

个晶圆表面47SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitaniumSilicideUnreactedTitaniumTiSi2形成•TiSi2形成–RTP工艺，N2

气氛，800℃–在Ti和Si接触的区域，形成TiSi2–其他区域的Ti没有变化–称为自对准硅化物工艺(Salicide)48SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTit

aniumSilicideTi刻蚀•Ti刻蚀–NH4OH+H2O2湿法刻蚀–未参加反应的Ti被刻蚀–TiSi2保留下来，形成Si和金属之间的欧姆接触49SiliconSubstrateP+SiliconEpiLayerP-P-W

ellN-WellN+DrainN+SourceP+DrainP+SourceBPSGBPSG淀积•硼磷硅玻璃(BPSG)淀积–CVD，厚度约1um–SiO2并掺杂少量硼和磷–改善薄膜的流动性和禁锢污染物的性能–这一层绝缘隔离器件和第一层金属50SiliconSu

bstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGBPSG抛光•硼磷硅玻璃(BPSG)抛光–CMP–在BPSG层上获得一个光滑的表

面51SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGPhotoresist光刻胶成形•光刻胶成形–用于定义接触孔(Contacts)–这是一个关键的

光刻步骤52SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGPhotoresist接触孔刻蚀•接触孔刻蚀–基于氟的RIE–获得垂直的侧墙–提供金属和底层器件

的连接53SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSG除去光刻胶54SiliconSubstra

teP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGTitaniumNitrideTiN淀积•TiN淀积–厚度约20nm–溅射工艺–有

助于后续的钨层附着在氧化层上55SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGTitaniumNitrideTungsten钨淀积•钨淀积–CVD–厚度不

少于接触孔直径的一半–填充接触孔56SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlug钨抛光•钨抛光–CMP–除去表面的钨和TiN–留下钨塞填充接触孔57

TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContact平面视图•完成接触孔，多晶硅上的接触孔没有出现在剖面图上58SiliconS

ubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1Ti(200Å)-electromigrationshuntTiN(500Å)-diffusionbarri

erAl-Cu(5000Å)-mainconductorTiN(500Å)-antireflectivecoatingMetal1淀积•第一层金属淀积(Metal1)–实际上由多个不同的层组成–溅射工艺59SiliconSubstrateP+SiliconEpiLayerP-P-We

llN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1Photoresist光刻胶成形•光刻胶成形–用于定义Metal1互连60SiliconSubstrateP+SiliconEpiLayerP-P-WellN-

WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistMetal1刻蚀•Metal1刻蚀–基于氯的RIE–由于Metal1由多层金属组成，所以需要多个刻蚀步骤61Silicon

SubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1除去光刻胶62TrenchOxidePolysiliconCross

SectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1平面视图•完成第一层互连63SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+Sou

rceP+DrainP+SourceBPSGWContactPlugMetal1IMD1IMD淀积•金属间绝缘体(IMD)淀积–未掺杂的SiO2–连续的CVD和刻蚀工艺，厚度约1um–填充在金属线之间，提供金属层之间的绝缘隔离64SiliconSubstrateP

+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1IMD抛光•IMD抛光–CMP65SiliconSubstrateP+SiliconEpiLayerP-P-

WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1Photoresist光刻胶成形•光刻胶成形–用于定义通孔(Vias)66SiliconSubstrateP+SiliconEp

iLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistIMD1通孔刻蚀•通孔刻蚀–基于氟的R

IE，获得垂直的侧墙–提供金属层之间的连接67SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1I

MD1除去光刻胶68TungstenSiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlu

gTiN和钨淀积•TiN和钨淀积–同第一层互连69SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal

1IMD1WViaPlug钨和TiN抛光•钨和TiN抛光–同第一层互连70TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMet

al1Via1平面视图•完成通孔71SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1

IMD1WViaPlugMetal2Metal2淀积•Metal2淀积–类似于Metal1–厚度和宽度增加，连接更长的距离，承载更大的电流72SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+Sourc

eP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistIMD1WViaPlugMetal2光刻胶成形•光刻胶成形–相邻的金属层连线方向垂直，减小层间的感应耦合73SiliconSubstrateP+SiliconEpiLayerP-

P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistIMD1WViaPlugMetal2Metal2刻蚀•Metal2刻蚀–类似

于Metal174SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1W

ViaPlugMetal2除去光刻胶75TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1Via1Met

al2平面视图•完成第二层互连，后面的剖面图将包括右上角的压焊点76SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMet

al1IMD1WViaPlugPassivationMetal2钝化层淀积•钝化层淀积–多种可选的钝化层，Si3N4、SiO2和聚酰亚胺等–保护电路免受刮擦、污染和受潮等77SiliconSubstrateP+SiliconEpiLayerP-P

-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlugPassivationBondPadPolyGateGa

teOxideSilicideSpacerMetal2钝化层成形•钝化层成形–压焊点打开，提供外界对芯片的电接触78CrossSectionTrenchOxideN+Source/DrainP+Source/DrainSpacerCo

ntactMetal1PolysiliconVia1+5VSupplyVOUTN-WellP-WellMetal2GroundBondPadVIN平面视图•完成，显示了电气连接和部分压焊点79完成80略有不同的另一个工艺流程Vth校正注入场氧化层TiN