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PresentedbyNinaMiaoNDC2004-02Ver.2.0.1.4PadstackDetails2.2.4Packageoutline.BoardDesign3.1BoardOutlineBoardDesign(Cont.)BoardDesign(Cont.)B

oardDesign(Cont.)BoardDesign(Cont.)4.3milsPrepreg~48milsCore：FR44.5milsPrepreg＝60Ω±10％。BoardDesign(C

ont.)LayoutProcess4.2Bringtheschematicdata4.3ImportlogicinformationLayoutProcess􀂄􀂄􀂄ConceptLogicImportThird-PartyLogicImport5.1Th

erearefourtypesofdesignrules:5.1.1SpacingRuleSet:Clearancesbetweenlines,pads,vias,andcopperareas(shapes)5

.1.2PhysicalRuleSet:Linewidthandlayerrestrictions5.1.3DesignConstraints:Packagechecks,soldermaskchecksandnegativeplaneislandchecks5.1.4Elect

ricalConstraintSets:Performancecharacteristics(crosstalkandpropagationdelay).􀂄􀂄6.1Theprerequisitesformanualplacementare:6.1.1Sy

mbols:Thepackagesymbolsandpadstacksrequiredforpartsinthenetlistmustexist.6.1.2Netlist:Youmustloadaschematicdatabaseintoan

Allegrodesignfile(.brd).6.1.3Floorplanning:Youcancreatea“blockdiagram”ofthelogicalfunctionsthatneedtobearrangedontheboardb

yusingRooms.6.ComponentPlacement(Cont.)􀂄Createroomsforfloorplanning.􀂄Assignreferencedesignatorsto"preplaced"devi

ces.􀂄PlaceI/Obounddevices.􀂄Placecriticallogicfunctions.􀂄Evaluateandreviseplacement.􀂄Placebulkdecouplingandbypasscaps.􀂄Usereport

stoaidplacementprocess.6.ComponentPlacement(Cont.)􀂄Placethemechanicalsymbol.􀂄Addformatsymbols.􀂄Addpackagesymb

ols.􀂄Setcolorandvisibility.􀂄Definethecrosssection(layerstackup).7.1InteractiveroutingmodesDefinenetpropertiesbeforeaddingetch.􀂄Commonnetpropertie

susedwithinteractiverouteare:MIN_LINE_WIDTHMIN_NECK_WIDTHNO_RATFIXED􀂄Addingsignalconnections􀂄Deletingsignalconnections􀂄Insertingv

ias.7.2AutomaticRoutingmodes􀂄􀂄􀂄9.1Bareboarda.Electricalcontinuitycheck(opensandshorts)b.PerformedafterfabricationAfterthephysi

calboardhasbeenmanufactured,itistestedforcontinuitybythefabricationfacility,knownasbareboardtest.Thistestchecksthec

onnectionsbetweenallcomponentpins,andensuresthatno“shorts”or“opens”exist.9.2In-circuita.Logicalperformancecheckb.Performedafterass

emblyQ&A