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PresentedbyNinaMiaoNDC2004-02Ver.2.0.1.4PadstackDetails2.2.4Packageoutline.BoardDesign3.1BoardOutlineBoardDesign(Cont.)BoardDesign(Cont.

)BoardDesign(Cont.)BoardDesign(Cont.)4.3milsPrepreg~48milsCore：FR44.5milsPrepreg＝60Ω±10％。BoardDesign(Cont.)Layou

tProcess4.2Bringtheschematicdata4.3ImportlogicinformationLayoutProcess􀂄􀂄􀂄ConceptLogicImportThird-P

artyLogicImport5.1Therearefourtypesofdesignrules:5.1.1SpacingRuleSet:Clearancesbetweenlines,pads,vias,andcopperareas(shapes)5.1.2PhysicalRuleSet

:Linewidthandlayerrestrictions5.1.3DesignConstraints:Packagechecks,soldermaskchecksandnegativeplaneislandchecks5.

1.4ElectricalConstraintSets:Performancecharacteristics(crosstalkandpropagationdelay).􀂄􀂄6.1Theprerequisitesformanualp

lacementare:6.1.1Symbols:Thepackagesymbolsandpadstacksrequiredforpartsinthenetlistmustexist.6.1.2Netlist:Youmustlo

adaschematicdatabaseintoanAllegrodesignfile(.brd).6.1.3Floorplanning:Youcancreatea“blockdiagram”ofthelogicalfunctions

thatneedtobearrangedontheboardbyusingRooms.6.ComponentPlacement(Cont.)􀂄Createroomsforfloorplanning.􀂄Assignreferencedesignators

to"preplaced"devices.􀂄PlaceI/Obounddevices.􀂄Placecriticallogicfunctions.􀂄Evaluateandreviseplacement.􀂄Placebulkdecouplingandbypasscaps.􀂄

Usereportstoaidplacementprocess.6.ComponentPlacement(Cont.)􀂄Placethemechanicalsymbol.􀂄Addformatsymbols.􀂄A

ddpackagesymbols.􀂄Setcolorandvisibility.􀂄Definethecrosssection(layerstackup).7.1Interactiverouting

modesDefinenetpropertiesbeforeaddingetch.􀂄Commonnetpropertiesusedwithinteractiverouteare:MIN_LINE_WIDTHMIN_NECK_WIDTHNO_RATFIXED􀂄Addings

ignalconnections􀂄Deletingsignalconnections􀂄Insertingvias.7.2AutomaticRoutingmodes􀂄􀂄􀂄9.1Bareboarda.Electricalcontin

uitycheck(opensandshorts)b.PerformedafterfabricationAfterthephysicalboardhasbeenmanufactured,itistestedforcontinuitybythefa

bricationfacility,knownasbareboardtest.Thistestcheckstheconnectionsbetweenallcomponentpins,andensuresthatno“sh

orts”or“opens”exist.9.2In-circuita.Logicalperformancecheckb.PerformedafterassemblyQ&A