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PresentedbyNinaMiaoNDC2004-02Ver.2.0.1.4PadstackDetails2.2.4Packageoutline.BoardDesign3.1BoardOutlineBoardDesign(Cont

.)BoardDesign(Cont.)BoardDesign(Cont.)BoardDesign(Cont.)4.3milsPrepreg~48milsCore：FR44.5milsPrepreg＝60

Ω±10％。BoardDesign(Cont.)LayoutProcess4.2Bringtheschematicdata4.3ImportlogicinformationLayoutProcess􀂄􀂄􀂄ConceptLogicImportThir

d-PartyLogicImport5.1Therearefourtypesofdesignrules:5.1.1SpacingRuleSet:Clearancesbetweenlines,pads,vias,andcopperareas(shapes)5.1.2PhysicalR

uleSet:Linewidthandlayerrestrictions5.1.3DesignConstraints:Packagechecks,soldermaskchecksandnegativeplaneislandchecks5.1.4ElectricalConstrai

ntSets:Performancecharacteristics(crosstalkandpropagationdelay).􀂄􀂄6.1Theprerequisitesformanualplacementare:6.1.1Symbols:Thepackagesymbolsa

ndpadstacksrequiredforpartsinthenetlistmustexist.6.1.2Netlist:YoumustloadaschematicdatabaseintoanAllegrodes

ignfile(.brd).6.1.3Floorplanning:Youcancreatea“blockdiagram”ofthelogicalfunctionsthatneedtobearrangedontheboardbyu

singRooms.6.ComponentPlacement(Cont.)􀂄Createroomsforfloorplanning.􀂄Assignreferencedesignatorsto"preplaced"devices

.􀂄PlaceI/Obounddevices.􀂄Placecriticallogicfunctions.􀂄Evaluateandreviseplacement.􀂄Placebulkdecouplingandbypasscaps.􀂄Usereportstoa

idplacementprocess.6.ComponentPlacement(Cont.)􀂄Placethemechanicalsymbol.􀂄Addformatsymbols.􀂄Addpackagesymbols.􀂄Setcolorandvisibility.�

�Definethecrosssection(layerstackup).7.1InteractiveroutingmodesDefinenetpropertiesbeforeaddingetch.􀂄Commonnetpropertiesusedwithinteract

iverouteare:MIN_LINE_WIDTHMIN_NECK_WIDTHNO_RATFIXED􀂄Addingsignalconnections􀂄Deletingsignalconnections􀂄Insertingvias.7.2Automa

ticRoutingmodes􀂄􀂄􀂄9.1Bareboarda.Electricalcontinuitycheck(opensandshorts)b.PerformedafterfabricationAfterthephysicalboardhasb

eenmanufactured,itistestedforcontinuitybythefabricationfacility,knownasbareboardtest.Thistestcheckstheconnectionsbe

tweenallcomponentpins,andensuresthatno“shorts”or“opens”exist.9.2In-circuita.Logicalperformancecheckb.Performed

afterassemblyQ&A